`timescale 1ns / 1ps

module SRLatch(
    input R, S,
    output reg Q,
    output wire Q_
);
    always @(R or S) begin
        case ({R, S})
            2'b01: Q <= 1'b1;  // Set
            2'b10: Q <= 1'b0;  // Reset
            2'b11: Q <= 1'bx;  // Invalid
             2'b00: Q<=Q;
        endcase
    end
assign Q_ = ~Q;
endmodule
